The VP880 and VP881 firmware board support package supports 3 different control interfaces:

1. VPX P1 PCIe to the FPGA

2. VPX VITA46.6 1000BASE-X primary control plane to the Zynq (UTP-1)

3. VPX VITA46.6 1000BASE-X secondary control plane to the FPGA (UTP-2)


UnitAPI by default supports communication through the first two interfaces. 

If 1000BASE-X TCP/IP access to the FPGA is required, UnitAPI needs to be reconfigured to scan for the FPGA IP address and configure the data and interrupt routers that are embedded in the FPGA host interface firmware star. 


Before applying changes to the UnitAPI configuration, customers should understand the firmware framework. 

Please carefully read the following documents that are part of the Board Support Package installation (VP880 or VP881 firmware must be decrypted and extracted):

- SD452 (axi_vp880_host_if).pdf or SD499 (axi_vp881_host_if).pdf 

- Applicable constellation documentation, for example: CD661 (VP880_N_AXI).pdf

- Software Board Support package documentation: UM080 r1.2 (VP880_VP881 Software BSP)


The axi_vp880/1_host_if documents show the data and interrupt routers embedded in the host interface. Depending on the physical interface type (PCIe, Zynq 1000BASE-X or FPGA 1000BASE-X), selected by the reference application, UnitAPI automatically configures those routers for the user (this is done by an underlying function that should not be confused with the unitapi_set_unit_datapath/unitapi_set_datapath functions). 

If UnitAPI needs to connect to the FPGA 1000BASE-X port, the following configuration modification is required:


1. Changing the IP range that UnitAPI scans to the FPGA IP address 192.168.1.11. 

    In file: "<location of BSP on file system>\4dsp\4FM Core Development Kit\Bins\Config\DeviceConfig.xml" change the line

      "<TcpIp first_ip="192.168.1.10" last_ip="192.168.1.10" port="1000"/>" 

    to

     "<TcpIp first_ip="192.168.1.11" last_ip="192.168.1.11" port="1000"/>"


2. Change the configuration of the data and interrupt routers in the FPGA host interface. 

    In file: "<location of BSP on file system>\4dsp\4FM Core Development Kit\Bins\Config\ConstellationPreConfig.xml"


    Search for the line with "<Constellation ID="661" interface_type="4">" where:

        - Constellation ID is the constellation ID of your design, in this example, CID661 is used

        - interface_type is 4 which is TCP/IP

    If the line with your constellation ID does not exist, create a new line with your constellation number (see example files attached).


For the VP880 host interface, apply the settings below:

    <StarCode uniqueID="452"><!--FPGA host star ID-->
        <Configuration address="544" value="-1"/><!--Clear AXI stream router-->
        <Configuration address="545" value="-1"/><!--Clear AXI stream router-->
        <Configuration address="546" value="-1"/><!--Clear AXI stream router-->
        <Configuration address="547" value="-1"/><!--Clear AXI stream router-->
        <Configuration address="512" value="1"/><!--Configure fpga irq routing to 1000BASE-X UTP2-->
        <Configuration address="546" value="3"/><!--Configure AXI stream router, connect data stream to 1000BASE-X UTP2 input  -->
        <Configuration address="547" value="2"/><!--Configure AXI stream router, connect 1000BASE-X UTP2 output to data stream -->
    </StarCode>


For the VP881 host interface, apply the settings below:

    <StarCode uniqueID="499"><!--FPGA host star ID-->
        <Configuration address="544" value="-1"/><!--Clear AXI stream router-->
        <Configuration address="545" value="-1"/><!--Clear AXI stream router-->
        <Configuration address="546" value="-1"/><!--Clear AXI stream router-->
        <Configuration address="547" value="-1"/><!--Clear AXI stream router-->
        <Configuration address="512" value="1"/><!--Configure fpga irq routing to 1000BASE-X UTP2-->
        <Configuration address="546" value="3"/><!--Configure AXI stream router, connect data stream to 1000BASE-X UTP2 input  -->
        <Configuration address="547" value="2"/><!--Configure AXI stream router, connect 1000BASE-X UTP2 output to data stream -->
    </StarCode>


Two example files are attached.


UnitAPI is now re-configured to communicate to the FPGA TCP/IP instead of the Zynq TCP/IP. Run any reference application with the 'interface type' argument set to select TCP/IP to connect with the FPGA.